Dear Author and Colleague,

DVCon 2004 is now acception proposals for technical papers, tutorials
and panels!

We encourage you to contribute your experiences with using hardware
design and verification languages, and to participate in the valuable
exchange of ideas.  

Details on submitting a paper, tutorial or panel proposal, along with
suggested topics, can be found on the Design and Verification Conference
web page, at http://www.dvcon.org

The deadline to submit a proposal for the technical session, panels or
tutorials is Wednesday, October 1, 2003!

Conference Schedule:
  Monday, March 1st      Half Day Tutorials
  Tuesday, March 2nd     Opening Session, Technical Sessions, 
                               Exhibits
  Wednesday, March 3rd   Technical Sessions, Exhibits

Please forward this e-mail your fellow engineers who may be interested
in participating or attending the conference.  We apologize if you
should happen to receive multiple copies of this message.

Sincerely,


Stephen Bailey  	
Program Chair					

		

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Dear Author and Colleague,

The Design and Verification Conference and Exposition, is THE place to
be if you see verification as the next big challenge in SOC.  At DAC
2003, it was THE major topic of the show, so you will have lots of
company. With more gates and more IP than ever, the key to putting it
all together can be summed up in one word "Verification". At DVCon 2004
you can hear, first hand, what design and verification engineers are
doing to achieve first pass, functional silicon.

There is frantic activity to accommodate engineers with language
standards that enable SOC, particularly in adopting very large blocks of
reusable IP. The road to usable standards is always bumpy, but the best
language standards are the ones that engineers define and use. Your
input at DVCon 2004 is vital as the new language standards roll out.

The environment could not be better at DVCon 2004 to showcase languages,
concepts, papers, panels, tutorials and vendor exhibits, all oriented
toward real results, functional chips, and profitable products. Be where
design engineers, verification engineers, EDA professionals, university
researchers, and industry pundits assemble to exchange ideas in design
and verification, the next big challenge in SOC.

We are happy to announce that DVCon will be held March 1-3, 2004 at the
DoubleTree Hotel in San Jose, California.

DVCon 2004 is now open for proposals for technical papers, tutorials and
panels!

We encourage you to contribute your experiences with using hardware
design and verification languages, and to participate in the valuable
exchange of ideas.  

Details on submitting a paper, tutorial or panel proposal, along with
suggested topics, can be found on the Design and Verification Conference
web page, at http://www.dvcon.org

The deadline to submit a proposal for the technical session, panels or
tutorials is Wednesday, October 1, 2003!

Conference Schedule:
  Monday, March 1st      Half Day Tutorials
  Tuesday, March 2nd     Opening Session, Technical Sessions, 
                            Exhibits
  Wednesday, March 3rd   Technical Sessions, Exhibits

Please forward this e-mail your fellow engineers who may be interested
in participating or attending the conference.  We apologize if you
should happen to receive multiple copies of this message.

Sincerely,


Stephen Bailey  	Frank Weiler
Program Chair		General Chair 
			

		
**********************************************************************
This is the list for the Accellera Member Announcements.

You have been subscribed to this list if you have either requested
Accellera membership or attended a Accellera sponsored conference. This
list is used to send periodic announcements on upcoming events and other
useful information.

If you would like to remove yourself from this list, please click:
http://mpassociates.post.intellimedia.com/UM/U.asp?B1031.12346.163.10274
and you will be removed immediately! Thank you!